This invention relates to MOS transistor circuits with a power-down functions, and more particularly, to such transistor circuits which include a "zero" threshold-mode MOS transistor. A "zero" threshold-mode transistor is a transistor which has a threshold voltage of approximately zero volts.
A "power-down function" is a feature which reduces the power consumption of a circuit when it is not active. MOS transistor circuits having power-down functions are now being used in integrated circuits (ICs).
A fertile area for such MOS circuits is the area of integrated circuit memory chips used in computer memory systems. Only a few memory chips are active during any computer memory access. The active chips, which are usually enabled by a chip select (CS) or chip enable (CE) signal, are said to be in an "operation" mode, while the inactive chips are said to be in a "standby" mode.
Some examples of MOS transistor circuits with power-down functions are shown in U.S. Pat. No. 4,096,584 to Owen III, et al.
The circuit shown in FIG. 2A of Owen III, et al. can be used in a static RAM system. This circuit uses a depletion-mode MOS transistor as a load, an enhancement-mode MOS transistor as a driver, and an enhancement-mode MOS transistor for a power-down function, the gate of the power-down transistor receiving a chip enable signal. The problem with this circuit is that the source of the MOS driver transistor is not easily brought to ground potential because of the significant voltage drop across the power-down MOS transistor.
In response to this problem, a "zero" threshold-mode MOS transistor was used in the circuit shown in FIG. 2B of Owen III, et al. and reproduced herein as FIG. 1A. The E/D inverter circuit shown in FIG. 1A uses depletion-mode MOS transistor Tr.sub.D1A as the load, enhancement-mode MOS transistor Tr.sub.E1A as the driver, and "zero" threshold-mode MOS transistor Tr.sub.P1A for a power down function.
MOS transistor Tr.sub.E1A has its source connected to ground, and its gate receives input signal V.sub.in. The drain of Tr.sub.E1A is connected to both the source and gate of transistor Tr.sub.D1A.
Transistor Tr.sub.P1A 's source is connected to Tr.sub.D1A 's drain, and the gate of Tr.sub.P1A receives circuit enable signal CS. Tr.sub.P1A 's drain connects to a voltage V.sub.cc.
The circuit in FIG. 1A is more suitable for integrated circuits than is the circuit shown in FIG. 2A of Owen III, et al. because of the "zero" threshold-mode transistor Tr.sub.P1A. Unfortunately, the E/D inverter circuit in FIG. 1A has its own problems when used in ICs. This circuit requires either that the load transistor Tr.sub.D1A be large or that the circuit's switching speed be slow. This characteristic is particularly disadvantageous when this circuit, i.e. one having a "zero" threshold-mode MOS transistor, is used in a Push-Pull inverter circuit which drives a large capacitive load.
An MOS Push-Pull inverter circuit similar to the inverter in FIG. 1A is shown in FIG. 1B. This Push-Pull inverter circuit used an E/D inverter circuit with a "zero" threshold-mode MOS transistor Tr.sub.E1B to provide a power-down function. The circuit also has a depletion-mode MOS transistor Tr.sub.D1B and an enhancement-mode MOS transistor Tr.sub.E1B.
The MOS transistor Tr.sub.E1B has its source connected to ground, and its gate to input signal V.sub.in. Transistor Tr.sub.D1B 's source connects to the drain of transistor Tr.sub.D1B, and the gate of Tr.sub.P1B receives the inverter input signal V.sub.in. The souce of Tr.sub.P1B is connected to the drain of Tr.sub.D1B. Tr.sub.P1B 's gate receives circuit enable signal CS, and its drain connects to voltage V.sub.cc.
This MOS Push-Pull inverter circuit, however, requires that transistor Tr.sub.P1B be unduly large to avoid slow switching speeds.